Arria 10, Arria V GZ, and Stratix V PCI Express Designs using the Avalon-ST Interface that Acess the Transaction Layer Configuration Space Signals (tl_cfg_*) May Hang - Arria 10, Arria V GZ, and Stratix V PCI Express Designs using the Avalon-ST Interface that Acess the Transaction Layer Configuration Space Signals (tl_cfg_*) May Hang Description The Transaction Layer Configuration Space Signals data (tl_cfg*) driven by the Hard IP for PCI Express are incorrectly sampled in the FPGA fabric. Consequently, a setup or hold time violation may occur. The Quartus Prime software does not report the violation because this multi-cycle path is not constrained. If a timing violation occurs, the system may hang. Resolution For Arria 10 devices, use Quartus Prime 16.0.1 or later. The Transaction Layer Configuration Space Signals interface is held for eight coreclkout_hip cycles. Your Application Layer RTL must include code to sample this interface in the middle of the eight-cycle window. See the example RTL below: //define register// reg [3:0] cfg_addr_reg; reg [3:0] captured_cfg_addr_reg; reg [31:0] captured_cfg_data_reg; reg cfgctl_addr_change; reg cfgctl_addr_change2; reg cfgctl_addr_strobe; // detect the address transition always @(posedge pld_clk or posedge reset) begin if (reset == 1\'b1) begin cfg_addr_reg <= 3\'h0; cfgctl_addr_change <= 1\'h0; cfgctl_addr_change2 <= 1\'h0; cfgctl_addr_strobe <= 1\'h0; end else begin cfg_addr_reg[3:0] <= tl_cfg_int_add[3:0]; // detect address change cfgctl_addr_change <= cfg_addr_reg[3:0] != tl_cfg_int_add[3:0]; // delay two clock and use as strobe to sample the input 32-bit data cfgctl_addr_change2 <= cfgctl_addr_change; cfgctl_addr_strobe <= cfgctl_addr_change2; end end // captured cfg ctl addr/data bus with the strobe always @(posedge pld_clk) if(cfgctl_addr_strobe) captured_cfg_addr_reg[3:0] <= tl_cfg_int_add[3:0]; captured_cfg_data_reg[31:0] <= tl_cfg_int_ctl[31:0]; end For Arria 10 devices, you must add the following timing constraints in your Synposys Design Constraints (SDC) file. set_multicycle_path -setup -through [get_pins -compatibility_mode -nocase {*|altpcie_a10_hip_pipen1b:altpcie_a10_hip_pipen1b|wys|tl_cfg_add[*]}] 2 set_multicycle_path -hold -through [get_pins -compatibility_mode -nocase {*|altpcie_a10_hip_pipen1b:altpcie_a10_hip_pipen1b|wys|tl_cfg_add[*]}] 2 set_multicycle_path -setup -through [get_pins -compatibility_mode -nocase {*|altpcie_a10_hip_pipen1b:altpcie_a10_hip_pipen1b|wys|tl_cfg_ctl[*]}] 2 set_multicycle_path -hold -through [get_pins -compatibility_mode -nocase {*|altpcie_a10_hip_pipen1b:altpcie_a10_hip_pipen1b|wys|tl_cfg_ctl[*]}] 2 For Stratix V and Arria V GZ devices, you must add the following timing constraints in your Synposys Design Constraints (SDC) file. set_multicycle_path -setup -through [get_pins -compatibility_mode -nocase {*|altpcie_a10_hip_pipen1b:stratixv_hssi_gen3_pcie_hip|tl_cfg_add[*]}] 2 set_multicycle_path -hold -through [get_pins -compatibility_mode -nocase {*|altpcie_a10_hip_pipen1b:stratixv_hssi_gen3_pcie_hip|tl_cfg_add[*]}] 2 set_multicycle_path -setup -through [get_pins -compatibility_mode -nocase {*|altpcie_a10_hip_pipen1b:stratixv_hssi_gen3_pcie_hip|tl_cfg_ctl[*]}] 2 set_multicycle_path -hold -through [get_pins -compatibility_mode -nocase {*|altpcie_a10_hip_pipen1b:stratixv_hssi_gen3_pcie_hip|tl_cfg_ctl[*]}] 2 Custom Fields values: ['novalue'] Troubleshooting novalue True ['PCI Express'] ['FPGA Dev Tools Quartus II Software'] novalue 13.1.1 ['Programmable Logic Devices'] ['novalue'] ['novalue'] ['novalue']