Interlaken IP - Interlaken is an interconnect protocol for high-speed, channelized chip-to-chip interface in networking applications. It is optimized for high-bandwidth chip-to-chip packet transfers at rates from 10… Altera, provides leadership programmable solutions that are easy-to-use and deploy in applications from the cloud to the edge, offering limitless AI possibilities. Our end-to-end broad portfolio of… Agilex™ 5 FPGA D-Series Agilex™ 5 FPGA E-Series Agilex™ 7 FPGA F-Series Agilex™ 7 FPGA I-Series Agilex™ 7 FPGA M-Series Agilex™ 9 FPGA Direct RF-Series Arria® 10 GT FPGA Arria® 10 GX FPGA Arria® 10 SX FPGA Stratix® 10 AX FPGA Stratix® 10 DX FPGA Stratix® 10 GX FPGA Stratix® 10 SX FPGA Stratix® 10 TX FPGA Stratix® V GS FPGA Stratix® V GX FPGA The Interlaken FPGA IP core is Interlaken Protocol Definition v1.2 compliant and allows system developers to achieve high-bandwidth throughput in their systems. This pre-built, ready-to-go IP building block shortens the design cycle resulting in faster time to market. Interlaken is an interconnect protocol for high-speed, channelized chip-to-chip interface in networking applications. It is optimized for high-bandwidth chip-to-chip packet transfers at rates from 10 Gbps to 600 Gbps and beyond. The Interlaken FPGA IP core is ideal for: 1) Multi-terabit routers and switches for access, 2) Carrier Ethernet and data center applications that demand IP configurability to optimize for various traffic profiles, and 3) Scalability for next-generation platforms. The Altera Interlaken IP Portfolio accomplishes major development milestones: third-generation soft IP (includes media access control (MAC)) and second-generation hardened IP (includes physical coding sublayer (PCS) / physical medium attachment (PMA)). These seasoned, battle-tested cores continue to provide the additional robustness and maturity required for new, more intelligent systems. Aerospace ASIC Proto Broadcast Data Center Cloud (Public, Private, Hybrid) Data Center OEM (IHV, ISV, SI, VAR) Defense Government Industrial Medical Test Transportation Wireless Interlaken IP Key Features Data rate selection up to 25.78125 Gbps (NRZ) OR 56 Gbps (PAM4) Offering Brief No No No No Encrypted Verilog Agilex™ 5 FPGA D-Series Agilex™ 5 FPGA E-Series Agilex™ 7 FPGA F-Series Agilex™ 7 FPGA I-Series Agilex™ 7 FPGA M-Series Agilex™ 9 FPGA Direct RF-Series Arria® 10 GT FPGA Arria® 10 GX FPGA Arria® 10 SX FPGA Stratix® 10 AX FPGA Stratix® 10 DX FPGA Stratix® 10 GX FPGA Stratix® 10 SX FPGA Stratix® 10 TX FPGA Stratix® V GS FPGA Stratix® V GX FPGA Yes Yes Offering Brief Production a1JUi0000049UV2MAM What's Included Encrypted Verilog source code Ordering Information IP-ILKN/50G; IP-ILKN/100G; IP-ILKN-2 Direct Mouser a1JUi0000049UV2MAM Production Intellectual Property (IP) a1MUi00000BO8twMAD a1MUi00000BO8twMAD 2026-04-21T12:58:34.000+0000 Interlaken is an interconnect protocol for high-speed, channelized chip-to-chip interface in networking applications. It is optimized for high-bandwidth chip-to-chip packet transfers at rates from 10 Gbps to 600 Gbps and beyond. Altera Solutions