Timing Violation On *mr_oversample* Path in Arria V HDMI 2.0 Design Example - Timing Violation On *mr_oversample* Path in Arria V HDMI 2.0 Design Example Description When you run the HDMI design files for Arria V devices ( av_sk_hdmi2 ) in the ACDS version 15.0, you will encounter timing violation issues on the *mr_rx_oversample:RX_OVERSAMPLE* path. Resolution There is no workaround for this issue. This issue is fixed in version 15.0 Update 1 of the HDMI IP core. Custom Fields values: ['novalue'] Troubleshooting novalue True ['novalue'] ['FPGA Dev Tools Quartus II Software'] novalue 15.0 ['Programmable Logic Devices'] ['novalue'] ['novalue'] ['novalue']