What is the state of General Purpose I/Os (GPIOs) after loading the periphery image when Configuration via Protocol (CvP) is used in the Stratix® 10 FPGA devices? - What is the state of General Purpose I/Os (GPIOs) after loading the periphery image when Configuration via Protocol (CvP) is used in the Stratix® 10 FPGA devices? Description In the Stratix® 10 FPGA devices, when the Configuration via Protocol (CvP) is used, the state of General Purpose I/Os (GPIOs) is tri-stated with weak pull-up after Power-On reset (POR) and until the core image is loaded. Once the core image is loaded, the state of the GPIOs will be according to the loaded design. Resolution This information is available starting with the Stratix® 10 Configuration via Protocol (CvP) Implementation User Guide document version 19.3. Custom Fields values: ['novalue'] Troubleshooting 14010192943 False ['novalue'] ['FPGA Dev Tools Quartus® Prime Software Pro'] No plan to fix 19.3 ['Stratix® 10 FPGAs and SoCs'] ['novalue'] ['novalue'] ['novalue']