Why does the High Bandwidth Memory (HBM2) Interface IP example design in the Intel® Stratix® 10 MX FPGA show min pulse width violation? - Why does the High Bandwidth Memory (HBM2) Interface IP example design in the Intel® Stratix® 10 MX FPGA show min pulse width violation? Description Due to a problem in the Intel® Quartus® Prime Pro Edition Software version 19.1 and earlier, you may see the min pulse width violation if you create an example design for the High Bandwidth Memory (HBM2) Interface IP targeting the Intel® Stratix® 10 MX FPGA. Resolution To work around this problem, download and install the Intel® Quartus® Prime Pro Edition Software version 19.1 patch 0.04 from the appropriate link below. After installing the patch , follow the steps shown in the Readme file. Download patch Quartus-19.1-0.04-windows.exe for Windows (.exe) Download patch Quartus-19.1-0.04-linux.run for Linux (.run) Download the Readme for patch Quartus-19.1-0.04-readme.txt (.txt) This problem is fixed starting with the Intel® Quartus® Prime Pro Edition Software version 19.2. Custom Fields values: ['novalue'] Troubleshooting 1409184691 False ['High Bandwidth Memory (HBM2) Interface IP'] ['FPGA Dev Tools Quartus® Prime Software Pro'] 19.2 19.1 ['Stratix® 10 FPGAs and SoCs', 'Stratix® 10 MX FPGA'] ['novalue'] ['novalue'] ['novalue']