Why am I unable to set the 'Size of address pages' to a value between 17 and 21 bits for the Intel® Arria® 10 FPGA and Intel® Cyclone® 10 GX FPGA Hard IP for PCI Express in Avalon® memory-mapped mode? - Why am I unable to set the 'Size of address pages' to a value between 17 and 21 bits for the Intel® Arria® 10 FPGA and Intel® Cyclone® 10 GX FPGA Hard IP for PCI Express in Avalon® memory-mapped mode? Description Due to a problem in the Intel® Quartus® Prime Standard Edition Software version 18.1 and later, address page sizes between 17 and 21 bits (inclusive) are not available for selection when using the Intel® Arria® 10 FPGA and Intel® Cyclone® 10 GX FPGA Hard IP for PCI Express in Avalon® memory-mapped mode with Avalon memory-mapped address width of 32 bits. Resolution This problem is fixed starting with the Intel® Quartus® Prime Standard Edition Software version 22.1. Custom Fields values: ['novalue'] Troubleshooting 14016264999 False ['Arria® 10 Cyclone® 10 Hard IP for PCI Express'] ['FPGA Dev Tools Quartus® Prime Software Standard'] 22.1 18.1 ['Arria® 10 FPGAs and SoCs', 'Cyclone® 10 GX FPGA'] ['novalue'] ['novalue'] ['novalue']