Why are RESPONSE packets from the RapidIO I/O Write Master dropped? - Why are RESPONSE packets from the RapidIO I/O Write Master dropped?
Description The RESPONSE packets to NWRITE_R packets may be dropped by the I/O Write Master within the RapidIO® MegaCore® function when there is insufficient bandwidth on the Transport Layer to transport the required RESPONSE packets. A round-robin arbitration scheme is used to grant access to the Transport Layer between the Avalon-ST Pass-Through Interface, Doorbell, I/O Slave, I/O Master and Maintenance ports. If another interface (e.g. I/O Slave) is transmitting packets, the RESPONSE egress rate from the I/O Master may be lower than the NWRITE_R ingress rate, which will lead to the RESPONSE being dropped. When a RESPONSE to an NWRITE_R is dropped, the PKT_RSP_TIMEOUT bit of the Logical/Transport Layer Error Detect CSR in the device that transmitted the NWRITE_R is asserted. Resolution 1) Ensure that the number of outstanding NWRITE_R transactions does not exceed 32. The I/O Master can store a maximum of 32 responses in its queue. 2) Set the timeout to an appropriate value, using the Port Response Time-Out Control CSR, to ensure that a dropped RESPONSE is detected quickly. If the timeout is not set then a dropped RESPONSE will cause the io_s_wr_waitrequest signal to stay asserted for the default 4.5 seconds. 3) If system ordering is not required, use an NWRITE, avoiding the need for a RESPONSE from the I/O Write Master.
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Troubleshooting
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['Arria® II GX FPGA', 'Arria® II GZ FPGA', 'Arria® V GT FPGA', 'Arria® V GX FPGA', 'Arria® V GZ FPGA', 'Arria® V ST FPGA', 'Arria® V SX FPGA', 'Cyclone® IV GX FPGA', 'Cyclone® V GT FPGA', 'Cyclone® V GX FPGA', 'Cyclone® V ST FPGA', 'Cyclone® V SX FPGA', 'Arria® 10 GT FPGA', 'Arria® 10 GX FPGA', 'Arria® 10 SX FPGA', 'Stratix® IV GT FPGA', 'Stratix® IV GX FPGA', 'Stratix® V GS FPGA', 'Stratix® V GT FPGA', 'Stratix® V GX FPGA']
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['novalue'] - 2021-08-25
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