How do I set the PLL compensation targets for the Altera_PLL megafunction? - How do I set the PLL compensation targets for the Altera_PLL megafunction? Description You will see the following warning in the Quartus ® II fitter report if a PLL does not have a compensated clock specified: Warning (177007): PLL(s) placed in location <PLL location> do not have a PLL clock to compensate specified - the Fitter will attempt to compensate all PLL clocks Info (177008): <instance_name> altera_pll:altera_pll_i|general[0].gpll~FRACTIONAL_PLL Resolution The way to specify a compensated clock target (which can be done directly in the ALTPLL megafunction GUI), is to make a “Match PLL Compensation Clock” assignment. The syntax of the PLL clock node has to be specific in order for it to be saved in the Assignment Editor. Filter on *outclk_wire* in a post compilation filter in the node finder. For example: example:inst|example_0002:example_inst|altera_pll:altera_pll_i|outclk_wire[0] Where outclk_wire[0] corresponds to C0 in the Altera_PLL instance. Related Articles Warning (177007): PLL(s) placed in location <PLL location> do not have a PLL clock to compensate specified - the Fitter will attempt to compensate all PLL clocks Custom Fields values: ['novalue'] Troubleshooting novalue False ['novalue'] ['FPGA Dev Tools Quartus II Software'] novalue 12.0 ['Arria® V GT FPGA', 'Arria® V GX FPGA', 'Arria® V GZ FPGA', 'Arria® V ST FPGA', 'Arria® V SX FPGA', 'Cyclone® V E FPGA', 'Cyclone® V GT FPGA', 'Cyclone® V GX FPGA', 'Cyclone® V SE FPGA', 'Cyclone® V ST FPGA', 'Cyclone® V SX FPGA', 'Stratix® V E FPGA', 'Stratix® V GS FPGA', 'Stratix® V GT FPGA', 'Stratix® V GX FPGA'] ['novalue'] ['novalue'] ['novalue']