Arria 10, Arria V GZ, and Stratix V PCI Express Designs using the Avalon-MM or Avalon-MM DMA Interface that Acess the Transaction Layer Configuration Space Signals (tl_cfg_*) May Hang - Arria 10, Arria V GZ, and Stratix V PCI Express Designs using the Avalon-MM or Avalon-MM DMA Interface that Acess the Transaction Layer Configuration Space Signals (tl_cfg_*) May Hang Description The Transaction Layer Configuration Space Signals data (tl_cfg*) driven by the Hard IP for PCI Express are incorrectly sampled in the FPGA fabric. Consequently, a setup or hold time violation may occur. The Quartus Prime software does not report the violation because this multi-cycle path is not constrained. If a timing violation occurs, the system may hang. Resolution This problem is fixed in version 16.0.1 or later of the Quartus Prime software. Custom Fields values: ['novalue'] Troubleshooting novalue True ['PCI Express'] ['FPGA Dev Tools Quartus II Software'] novalue 13.1.1 ['Programmable Logic Devices'] ['novalue'] ['novalue'] ['novalue']