When using the R-Tile Avalon® Streaming FPGA IP for PCI Express* in PIPE Direct Mode, why do I observe unexpected rxdatavalid toggling after P1 to P0 transition? - When using the R-Tile Avalon® Streaming FPGA IP for PCI Express* in PIPE Direct Mode, why do I observe unexpected rxdatavalid toggling after P1 to P0 transition? Description Due to a problem in Quartus® Prime Pro version 24.1 and earlier, when using the R-Tile Avalon® Streaming FPGA IP for PCI Express* in PIPE Direct Mode, unexpected toggling may be observed on the rxdatavalid signal when transitioning from a low power state (P1) to a normal operation (P0). This problem may also impact the symbol lock in the PCS block. Devices Affected are listed below: AGIx019R18Axxxxx AGIx023R18Axxxxx AGIx022R29Axxxxx AGIx027R29Axxxxx AGIx022R31Axxxxx AGIx027R31Axxxxx AGIx041R29Dxxxxx Resolution No workaround for this problem exists. Link re-training is required. This problem has been fixed in version 24.2 of the Quartus® Prime Pro Edition Software. Custom Fields values: ['novalue'] Troubleshooting 15012624900 False ['R-Tile Avalon-ST for PCI Express'] ['FPGA Dev Tools Quartus® Prime Software Pro'] 24.2 22.4 ['Agilex™ 7 FPGA I-Series'] ['novalue'] ['novalue'] ['novalue']