Why is the width of DDR3 Avalon interface signal "local_rdata_error" 4 bits? - Why is the width of DDR3 Avalon interface signal "local_rdata_error" 4 bits? Description When you generate a DDR3 UniPHY IP controller with the option "Enable Error Detection and Correction Logic" turned ON, a 4 bit error output signal, local_rdata_error [3:0], will be generated in 11.1SP2 and older IP versions. All 4 bits behave the same and o nly bit 0 of local_rdata_error signal should be monitored. The other 3 bits can be ignored. Resolution This issue will be fixed in a future release of Quartus® II software and IP. Custom Fields values: ['novalue'] Troubleshooting novalue False ['novalue'] ['FPGA Dev Tools Quartus II Software'] novalue 11.1 ['Stratix® IV GX FPGA'] ['novalue'] ['novalue'] ['novalue']