Why DDR3 ODT fails in simulation with denali? - Why DDR3 ODT fails in simulation with denali? Description In the DDR3 SDRAM Controllers with ALTMEMPHY IP MegaCore® functions version 11.0 and earlier, DDR3 ODT failures can occur in simulation with Denali. Affected Configurations This issue affects DDR3 configurations with unbuffered DIMM, multiple DIMMs, ODT enabled, and a number of slots greater than 1. Design Impact This issue can result in a simulation error, and can also result in data corruption in hardware. Solution Status This issue is fixed in the DDR3 SDRAM Controllers with ALTMEMPHY IP MegaCore function version 11.0 SP1. Resolution There are two possible workarounds for this issue: Option 1: Open the alt_mem_ddrx_controller_st_top.v file and add 1 (clk) to the equation used to derive the localparams CFG_EXTRA_CTL_CLK_RD_TO_WR_DIFF_CHIP and CFG_EXTRA_CTL_CLK_WR_TO_RD_DIFF_CHIP. Option 2: Open the generated file <variation_name>_alt_mem_ddrx_controller_top.v and change the localparam CFG_READ_ODT_CHIP value to ‘h0 . Custom Fields values: ['novalue'] Troubleshooting novalue True ['novalue'] ['FPGA Dev Tools Quartus II Software'] 11.0.1 10.0 ['Programmable Logic Devices'] ['novalue'] ['novalue'] ['novalue']