How is the voltage selected for the VCCRSTCLK_HPS pin in the Pin-Out File (.pin) generated by the Quartus® II software? - How is the voltage selected for the VCCRSTCLK_HPS pin in the Pin-Out File (.pin) generated by the Quartus® II software? Description When using Cyclone® V or Arria® V devices that support the Hard Processor System (HPS), the .pin file created by the Quartus® II software will select from various voltages for the VCCRSTCLK_HPS pin. Supported voltages are 1.8V, 2.5V, 3.0V, and 3.3V. The Quartus® II software does not allow you to specify the voltage for the clock and reset pins in the HPS that use the VCCRSTCLK_HPS supply. Instead, you must connect a supported voltage to the VCCRSTCLK_HPS pin based on the requirements of the I/O standard used by the HPS clock and reset pins (HPS_CLK1, HPS_CLK2, HPS_nRST, HPS_nPOR, and HPS_PORSEL). The voltage shown for the VCCRSTCLK_HPS pin in the .pin file is based on the FPGA configuration I/O voltage selected for the device project. If no configuration voltage is selected, the .pin file will show 1.8V/2.5V/3.0V/3.3V for the VCCRSTCLK_HPS pin. However, if a configuration I/O voltage is selected, the .pin file will show the same voltage on VCCRSTCLK_HPS as VCCPGM. There is no requirement to have VCCRSTCLK_HPS powered by the same voltage as VCCPGM. However, you must connect the VCCRSTCLK_HPS pin to a voltage based on the requirements of the I/O standard used by the HPS clock and reset pins. Resolution The problem has been fixed in Quartus® II software version 14.0. Custom Fields values: ['novalue'] Troubleshooting 2205814708 False ['novalue'] ['FPGA Dev Tools Quartus II Software'] 14.0 13.0 ['Arria® V ST FPGA', 'Arria® V SX FPGA', 'Cyclone® V SE FPGA', 'Cyclone® V ST FPGA', 'Cyclone® V SX FPGA'] ['novalue'] ['novalue'] ['novalue']