Why is the afi_half_clk signal not constrained in my UniPHY-based memory controller? - Why is the afi_half_clk signal not constrained in my UniPHY-based memory controller? Description Due to a problem in the Quartus® II software version 12.1 and later, UniPHY-based memory controllers are missing SDC constraints to properly constrain the afi_half_clk clock leading to incorrect timing analysis for the afi_half_clk clock domain. Resolution If the design is not using the afi_half_clk signal, no changes need to be made. If the design uses the afi_half_clk signal, add a create_generated_clock assignment for afi_half_clock to the top-level SDC file. If there is no top-level SDC file, create one and add it to the project file list. This issue has been fixed in Intel® Quartus® Prime Edition Software version 13.1 Custom Fields values: ['novalue'] Troubleshooting 2205801479 False ['novalue'] ['FPGA Dev Tools Quartus II Software'] 13.1 12.1 ['Arria® V GT FPGA', 'Arria® V GZ FPGA', 'Arria® V ST FPGA', 'Arria® V SX FPGA', 'Cyclone® V E FPGA', 'Cyclone® V GT FPGA', 'Cyclone® V GX FPGA', 'Cyclone® V SE FPGA', 'Cyclone® V ST FPGA', 'Stratix® IV GT FPGA', 'Stratix® IV GX FPGA', 'Stratix® V E FPGA'] ['novalue'] ['novalue'] ['novalue']