Stratix® 10 GX FPGAs - View Stratix 10 GX FPGA and find product specifications, features, applications and more. Product Pages Broadcast Test Wireline Overview Stratix 10 GX FPGAs contain up to 10.2 million logic elements and feature 96 general-purpose transceivers across separate chiplets. With 2,666 Mbps DDR4 external memory interface performance, these devices are optimized for FPGA applications requiring maximum transceiver throughput, I/O bandwidth, and core fabric performance. Stratix 10 GX FPGA Product Table Benefits Stratix 10 FPGAs and SoC FPGAs use the Hyperflex™ core architecture, delivering higher throughput, improved power efficiency, enhanced design functionality, and increased developer productivity over previous-generation devices. High Clock Performance and Lower Power Consumption The Hyperflex™ FPGA Architecture introduces bypassable Hyper-Registers throughout the FPGA fabric—on interconnect routing segments and at the inputs of all functional blocks. These Hyper-Registers enable three advanced techniques to optimize core performance: Hyper-Retiming reduces critical path delays; Hyper-Pipelining improves timing closure by minimizing routing congestion; and Hyper-Optimization enhances overall device performance by enabling more aggressive timing and resource utilization strategies. Runs on the Hyperflex™ FPGA Architecture The patented Embedded Multi-Die Interconnect Bridge (EMIB) technology provides high-density interconnect between heterogeneous dies in the same package. It enables in-package functionality that was previously too complex or cost-prohibitive to implement using traditional multi-die packaging methods. Enabling Next-Generation Chiplets Using 3D System-in-Package Technology Key Features The core architecture delivers many advantages: higher throughput, improved power efficiency, greater design functionality, increased designer productivity and incorporates bypassable hyper-registers. Hyperflex™ FPGA Architecture The transceivers are on the heterogeneous 3D System-in-Package (SiP) transceiver tiles, each containing 24 full-duplex transceiver channels offering solutions for connectivity needs and future flexibility and scalability needs as data rates, modulation schemes, and protocol IPs evolve. Heterogeneous 3D SiP Transceiver Tiles SDM controls key operations, such as configuration, device security, single event upset (SEU) responses, and power management. It creates a unified, secure management system for the entire device, including the FPGA fabric, hard processor system (HPS) in SoCs, embedded hard IP blocks, and I/O blocks. Secure Device Manager (SDM) Applications Wireline Test and Measurement Broadcast and Pro AV Dev Kits, IP, Example Designs & Software Get Started: Development Kits, IP, Example Designs and Software Dev Kit Stratix® 10 GX FPGA Signal Integrity Development Kit (L-TILE) Features the Stratix 10 GX L-Tile FPGA (1SG280LU2F50E2VG) with transceiver performance up to 17.4 Gbps (L-Tile) Stratix® 10 GX FPGA Signal Integrity Development Kit (H-TILE) Features the Stratix 10 GX H-Tile FPGA (1SG280HU1F50E2VG) with transceiver performance up to 28.3 Gbps (H-Tile) IP Stratix 10 FPGA H-Tile Hard IP for Ethernet The IP core configures the transceivers to implement the relevant specification for your IP core variation. 10GBASE-R PHY FPGA IP The 10GBASE-R PHY FPGA Intellectual Property (IP) core allows connectivity directly with any XFP or SFP+ optical module or with any external device with XFI and SFI interfaces. Example Designs FPGA Developer Site GitHub site that provides a single location for developers to find and use Altera example designs, software, drivers, and associated collateral. Example Design Store This site offers essential FPGA developer resources—including example designs, documentation, and software tools—to accelerate your design process and reduce time to production. Software Quartus® Prime Pro Edition Design Software Documentation Documents Documentation Stratix 10 GX FPGA Product Table Stratix 10 FPGAs and SoCs Quick Links Stratix 10 GX FPGA Device Overview Stratix 10 FPGA Datasheet Support Resources Stratix® 10 GX FPGA - 2026-03-10

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