Serial Digital Interface I Design Long Locking Time in 40nm Devices - Serial Digital Interface I Design Long Locking Time in 40nm Devices Description The Serial Digital Interface (SDI) I design has long locking time when switching from high definition (HD) to third-generation (3G) or when the core is reset after receiving 3G. The design takes a longer time to achieve frame lock when the rate detection block cannot detect the standard correctly because the data recovered during the rate detection is incorrect. This issue affects the SDI I design in 40nm devices. Resolution There is no workaround for this issue. This issue will be fixed in a future version. Custom Fields values: ['novalue'] Troubleshooting novalue True ['novalue'] ['FPGA Dev Tools Quartus II Software'] novalue 12.0 ['Programmable Logic Devices'] ['novalue'] ['novalue'] ['novalue']