How do I simulate bi-directional signals with dynamic OCT with the Quartus® II software generated IBIS file ? - How do I simulate bi-directional signals with dynamic OCT with the Quartus® II software generated IBIS file ? Description For software versions before Quartus II 13.1, the flow for simulating the input side of a bidirectional pin with dynamic on chip termination (OCT) is described in solution: www.intel.com/content/www/us/en/support/programmable/articles/000081259.html For V series FPGAs (Stratix® V, Arria® V, and Cyclone® V) in the Quartus® II software v13.1, if you are using bidirectional I/O with dynamic OCT, the Quartus II software-generated IBIS file includes models of both the output and input terminations. This is supported for IBIS model versions of 4.2 and later. Dynamic OCT is used where a signal uses a series on-chip termination during output operation and a parallel on-chip termination during input operation. Typically this is used in External Memory Interface IP. The Quartus II software v13.1 dynamic OCT IBIS models have a name ending with "g50c_r50c". For example : sstl15i_ctnio_g50c_r50c. In the simulation tool, the IBIS model is attached to a buffer: When the buffer is assigned as an output, the series termination (r50c) is used When the buffer is assigned as an input, the parallel termination (g50c) is used Resolution This is planned to be documented in a future version of the Quartus II Handbook. Custom Fields values: ['novalue'] Troubleshooting 2205756400 False ['novalue'] ['FPGA Dev Tools Quartus II Software'] 14.0 13.1 ['Arria® V GT FPGA', 'Arria® V GX FPGA', 'Arria® V GZ FPGA', 'Arria® V ST FPGA', 'Arria® V SX FPGA', 'Cyclone® V E FPGA', 'Cyclone® V GT FPGA', 'Cyclone® V GX FPGA', 'Cyclone® V SE FPGA', 'Cyclone® V ST FPGA', 'Cyclone® V SX FPGA', 'Stratix® V E FPGA', 'Stratix® V GS FPGA', 'Stratix® V GT FPGA', 'Stratix® V GX FPGA'] ['novalue'] ['novalue'] ['novalue']