Stratix V Hard IP for PCI Express IP Core Gen3 x8 app_rstn Timing Issue - Stratix V Hard IP for PCI Express IP Core Gen3 x8 app_rstn Timing Issue
Description The Stratix V Hard IP for PCI Express IP Core Gen3 x8 example design has timing failures related to the app_rstn signal. Resolution This issue is fixed in release 13.0 of the Quartus II software.
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Troubleshooting
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True
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['FPGA Dev Tools Quartus II Software']
13.0
12.0
['Stratix® V FPGAs']
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['novalue']
['novalue'] - 2021-08-25
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