Why does the F-Tile Dynamic Reconfiguration Suite Intel® IP Design Example using VHDL fail to simulate correctly when using the Cadence® Xcellium simulator? - Why does the F-Tile Dynamic Reconfiguration Suite Intel® IP Design Example using VHDL fail to simulate correctly when using the Cadence® Xcellium simulator? Description Due to a problem in the Intel® Quartus® Prime Pro Edition Software version 22.1, the VHDL design example implementation of the F-Tile Dynamic Reconfiguration Suite Intel® IP fails to simulate correctly. The Cadence® Xcellium simulator will generate warnings related to the dr_cpu_ctrl_inst module containing text similar to that shown below: Attempted propagation of defparam results to a non-Verilog instance Resolution To work around this problem in simulation, edit the run_xcelium.sh file to add a new -generic switch to force and set the dr_cpu_ctrl DMEM_INIT_FILE with the correct *_combined mif file generated from QTLG flow. Note: Ensure that the correct mif file name has been used only after the Quartus Support-logic Generation stage has run. An example of the required assignment is shown below: xmelab -relax -timescale '1 ps / 1 ps' -access +rwc -generic "basic_avl_tb_top.eth_f_hw.dr_dut:dr_f_0.dr_cpu_ctrl_inst:DMEM_INIT_FILE => \"eth_f_hw__combined_z1577a_x0_y166_n0.mif\"" basic_avl_tb_top This problem is scheduled to be fixed in a future release of the Intel® Quartus® Prime Pro Edition Software. Custom Fields values: ['novalue'] Errata 15010642131 False ['Interfaces'] ['FPGA Dev Tools Quartus® Prime Software Pro'] 22.2 22.1 ['Agilex™ 7 FPGA I-Series'] ['novalue'] ['novalue'] ['novalue']