Signal Tap Logic Analyzer: Basic Configuration & Trigger Conditions - 35 Minutes This training is part 2 of 4. The Signal Tap embedded logic analyzer (ELA) is a system-level debugging tool that monitors the state of internal FPGA design signals and triggers on custom, user-defined conditions during run-time operation of the device without having to bring signals out to device I/O pins. It integrates directly into your design, making it easy to perform functional debug. This part of the training goes into detail on how to create basic trigger conditions. It then walks through many of the options found in the Signal Configuration section of the tool, including the selection of a sampling clock, choosing buffer options, and the many ways of performing sample storage qualification. Course Objectives At course completion, you will be able to: Set up basic trigger conditions including Basic And, Basic Or, and comparison triggers Choose options such as buffer type and configuration, pipelining, and storage qualification Skills Required Basic knowledge of the Altera® Quartus® Prime Software Knowledge of external logic analyzer operations (optional) If the audio for the course does not start automatically, press pause and then play on the course player. The transcript of the course audio is available in the Notes or closed captioning (CC) feature of the player. If you need assistance with this course, please email fpgatraining@altera.com . Reference Course Code: FPGA_ODSW1171. FPGA_ODSW1171. <p>Signal Tap Logic Analyzer: Basic Configuration & Trigger Conditions</p>