How do I use the CONFIG_SEL pin as a regular I/O pin in Intel® MAX® 10 devices with compact features? - How do I use the CONFIG_SEL pin as a regular I/O pin in Intel® MAX® 10 devices with compact features? Description In Intel® MAX® 10 devices, it is possible to use the CONFIG_SEL pin as a regular I/O pin when the Enable CONFIG_SEL pin option is not enabled. In Intel® MAX® 10 devices with compact features (feature option SC and DC), the Enable CONFIG_SEL pin option has been removed from Device and Pin Options because these devices don’t support dual configuration image mode. However, after the removal of this option, the Enable CONFIG_SEL pin option is still being set by default in the Intel® Quartus® Prime Software and you will see the following error message during compilation when assigning an I/O to the CONFIG_SEL pin: Error (176310): Can't place multiple pins assigned to pin location <pin location> (IOPAD_X<cordinate>_Y<cordinate>_N<number>) Resolution To work around this, add the following assignment into the Quartus Setting File (.qsf): set_global_assignment -name ENABLE_BOOT_SEL_PIN OFF This problem is fixed in version 22.1 of the Intel® Quartus® Prime Standard Edition Software. Custom Fields values: ['novalue'] Troubleshooting 14012692319 False ['novalue'] ['FPGA Dev Tools Quartus® Prime Software Standard'] 22.1 19.1 ['MAX® 10 10 FPGAs'] ['novalue'] ['novalue'] ['novalue']