Why there is no TX output when simulating IrDA UART IP? - Why there is no TX output when simulating IrDA UART IP? Description Due to a bug in IrDA UART simulation model, data is not loaded from FIFO to IrDA TX output. This is due to the calculation of the baud rate counters, when the max count was a power of 2. Resolution This problem has been fixed in the Quartus® Prime Standard edition software version 16.0. Custom Fields values: ['novalue'] Troubleshooting FB: 412121; False ['IrDA UART IP'] ['FPGA Dev Tools Quartus® Prime Software Pro'] 16.0 15.1 ['Programmable Logic Devices'] ['novalue'] ['novalue'] ['novalue']