Why do I see multiple warnings "Warning: NUMERIC_STD.TO_SIGNED: vector truncated" when simulating the FIR II Intel® FPGA IP Core? - Why do I see multiple warnings "Warning: NUMERIC_STD.TO_SIGNED: vector truncated" when simulating the FIR II Intel® FPGA IP Core? Description These warnings occur during simulation due to the representation of the constant (9) as a 4-bit signed vector in the FIR II Intel® FPGA IP VHDL file, hb1s_altera_fir_compiler_ii_1911_kmsq6ua_rtl_core.vhd. Number 9 cannot fit in a 4-bit signed number; hence, we see the vector_truncated warning from the TO_SIGNED VHDL function. When we interpret the bit pattern of 9 (1001) as a 4-bit signed number, we get -7. Resolution Make the following RTL modification to remove the "vector truncated" warning if you are using the Intel® Quartus® Prime Pro Edition Software version 22.3 or earlier. Find hb1s_altera_fir_compiler_ii_1911_kmsq6ua_rtl_core.vhd file in the following IP generated folder: <ip_variation_name>folder/altera_fir_compiler_ii_1911/sim/ Replace: u0_m0_wo0_wi0_r0_ra0_count1_inner(COUNTER,25)@14 low=-1, high=6, step=-1, init=5 u0_m0_wo0_wi0_r0_ra0_count1_inner_clkproc: PROCESS (clk) BEGIN IF (clk'EVENT AND clk = '1') THEN IF (areset = '1') THEN u0_m0_wo0_wi0_r0_ra0_count1_inner_i <= TO_SIGNED(5, 4); ELSE IF (u0_m0_wo0_memread_fanout_reg0_q = "1") THEN IF (u0_m0_wo0_wi0_r0_ra0_count1_inner_i(3 downto 3) = "1") THEN u0_m0_wo0_wi0_r0_ra0_count1_inner_i <= u0_m0_wo0_wi0_r0_ra0_count1_inner_i - 9; ELSE u0_m0_wo0_wi0_r0_ra0_count1_inner_i <= u0_m0_wo0_wi0_r0_ra0_count1_inner_i - 1; END IF; END IF; END IF; END IF; END PROCESS; with (changes in red): u0_m0_wo0_wi0_r0_ra0_count1_inner(COUNTER,25)@14 low=-1, high=6, step=-1, init=5 u0_m0_wo0_wi0_r0_ra0_count1_inner_clkproc: PROCESS (clk) variable wider_var : SIGNED (4 downto 0); BEGIN IF (clk'EVENT AND clk = '1') THEN IF (areset = '1') THEN u0_m0_wo0_wi0_r0_ra0_count1_inner_i <= TO_SIGNED(5, 4); ELSE IF (u0_m0_wo0_memread_fanout_reg0_q = "1") THEN IF (u0_m0_wo0_wi0_r0_ra0_count1_inner_i(3 downto 3) = "1") THEN wider_var := resize (u0_m0_wo0_wi0_r0_ra0_count1_inner_i, 5 ) - 9; ELSE wider_var := resize (u0_m0_wo0_wi0_r0_ra0_count1_inner_i, 5 ) - 1; END IF; u0_m0_wo0_wi0_r0_ra0_count1_inner_i <= wider_var(3 downto 0); END IF; END IF; END IF; END PROCESS; Note that there is another copy of this file in the synth folder: <ip_variation_name>folder/altera_fir_compiler_ii_1911/synth/hb1s_altera_fir_compiler_ii_1911_kmsq6ua_rtl_core.vhd The "sim" copy is used for the simulator. The Intel® Quartus® Prime software uses the "synth" copy. Technically, only the sim version of the files needs to be modified to fix the simulator warnings. This problem is fixed in version 22.4 of the Intel® Quartus® Prime Pro Edition Software. Custom Fields values: ['novalue'] Troubleshooting 16017335661 False ['FIR II IP'] ['FPGA Dev Tools Quartus® Prime Software Pro'] 22.4 22.3 ['Agilex™ 7 FPGA I-Series'] ['novalue'] ['novalue'] ['novalue']