Why isn't LVDS on the supported I/O Standards on the F-Tile FGT Reference Clock Input Specifications? - Why isn't LVDS on the supported I/O Standards on the F-Tile FGT Reference Clock Input Specifications? Description Due to the electrical charactersitics of the FGT reference clock input buffer, it is not fully compatible with the LVDS Standard Resolution LVDS Drivers are partially supported under a specific Voltage range and coupling. On-board AC-coupling 0.6 V ≤ VREFIN-DIFF ≤ 1.7 V Custom Fields values: ['novalue'] Troubleshooting 18030909798 False ['novalue'] ['novalue'] novalue novalue ['Agilex™ 7 FPGAs and SoCs'] ['novalue'] ['novalue'] ['novalue']