Is it possible to independently set the SCL and SDA falling times of the HPS I2C controller? - Is it possible to independently set the SCL and SDA falling times of the HPS I2C controller? Description The HPS I2C controller supports the SCL and SDA falling time configurable function. Resolution About how to implement the configuration in Linux* OS, please refer to the link: https://github.com/altera-opensource/linux-socfpga/commit/7d0429364bf0c0e69bf192362d85076e6ee9abd7 . The designer can configure the SCL and SDA falling time parameters in the dts file, such as: i2c-sda-falling-time-ns = <6000>; /* appended from boardinfo */ i2c-scl-falling-time-ns = <6000>; /* appended from boardinfo */ The SCL and SDA falling time configurable information has been added to the Arria® 10 Hard Processor System Technical Reference Manual . Custom Fields values: ['novalue'] Troubleshooting FB: 447797; False ['External Memory Interfaces Arria® 10 FPGA IP'] ['FPGA Dev Tools Quartus® Prime Software Pro'] novalue 17.0 ['Arria® V ST FPGA', 'Arria® V SX FPGA', 'Cyclone® V SE FPGA', 'Cyclone® V ST FPGA', 'Cyclone® V SX FPGA', 'Arria® 10 SX FPGA', 'Stratix® 10 SX FPGA'] ['novalue'] ['novalue'] ['novalue']