Why does the eCPRI IP assert mac_source_sop and mac_source_valid after the mac_source_ready is de-asserted? - Why does the eCPRI IP assert mac_source_sop and mac_source_valid after the mac_source_ready is de-asserted? Description Due to the ready latency of the eCPRI IP's mac_source_ready is 3 clock cycles, you may observe the mac_source_sop and mac_source_valid are asserted after the mac_source_ready is de-asserted. Resolution This is an expected behavior of the IP. This information has been updated in the eCPRI IP User Guide. Custom Fields values: ['novalue'] Troubleshooting 1508722677 False ['Interfaces Communications CPRI (Primary)'] ['FPGA Dev Tools Quartus® Prime Software Pro'] 21.2 20.1 ['Arria® 10 FPGAs and SoCs', 'Stratix® 10 FPGAs and SoCs'] ['novalue'] ['novalue'] ['novalue']