Leveraging AI Agents for SoC Verification - This course prepares system architects, hardware engineers, and software engineers to apply AI agents and large language model (LLM) technology directly within their System-on-Chip (SoC) verification… FPGA Authority is an Altera® certified trainer that provides in-depth, technically detailed instruction covering the complete FPGA and SoC design process. Training spans RTL hardware design, embedded… Agilex™ 3 FPGA C-Series Agilex™ 5 FPGA D-Series Agilex™ 5 FPGA E-Series Agilex™ 7 FPGA F-Series Agilex™ 7 FPGA I-Series Agilex™ 7 FPGA M-Series Agilex™ 9 FPGA Direct RF-Series Arria® 10 Bare Die Arria® 10 GT FPGA Arria® 10 GX FPGA Arria® 10 SX FPGA Arria® V GT FPGA Arria® V GX FPGA Arria® V GZ FPGA Arria® V ST FPGA Arria® V SX FPGA Cyclone® 10 GX FPGA Cyclone® 10 LP FPGA Cyclone® IV E FPGA Cyclone® IV GX FPGA Cyclone® V E FPGA Cyclone® V GT FPGA Cyclone® V GX FPGA Cyclone® V SE FPGA Cyclone® V ST FPGA Cyclone® V SX FPGA MAX® 10 FPGA Stratix® 10 AX FPGA Stratix® 10 Bare Die Stratix® 10 GX FPGA Stratix® 10 SX FPGA Stratix® 10 TX FPGA This course prepares system architects, hardware engineers, and software engineers to apply AI agents and large language model (LLM) technology directly within their System-on-Chip (SoC) verification flows. Participants move from first principles to production ready pipelines, learning how AI agents can automate testbench generation, constrained random stimulus creation, assertion writing, formal verification setup, debug triage, and coverage closure — all within an industry standard UVM methodology. The course blends conceptual instruction with hands on labs. Each lab session uses a realistic SoC subsystem design (AXI4 based interconnect with peripheral IP blocks) so that every AI agent capability is demonstrated in a verification context that reflects real project conditions. By the end of the course attendees will have built, evaluated, and deployed an end to end AI assisted verification pipeline. Access Aerospace ASIC Proto Broadcast Consumer Data Center Cloud (Public, Private, Hybrid) Data Center OEM (IHV, ISV, SI, VAR) Defense Government Industrial Medical Test Transportation Wireless Leveraging AI Agents for SoC Verification Key Features Offering Brief No No No No Agilex™ 3 FPGA C-Series Agilex™ 5 FPGA D-Series Agilex™ 5 FPGA E-Series Agilex™ 7 FPGA F-Series Agilex™ 7 FPGA I-Series Agilex™ 7 FPGA M-Series Agilex™ 9 FPGA Direct RF-Series Arria® 10 Bare Die Arria® 10 GT FPGA Arria® 10 GX FPGA Arria® 10 SX FPGA Arria® V GT FPGA Arria® V GX FPGA Arria® V GZ FPGA Arria® V ST FPGA Arria® V SX FPGA Cyclone® 10 GX FPGA Cyclone® 10 LP FPGA Cyclone® IV E FPGA Cyclone® IV GX FPGA Cyclone® V E FPGA Cyclone® V GT FPGA Cyclone® V GX FPGA Cyclone® V SE FPGA Cyclone® V ST FPGA Cyclone® V SX FPGA MAX® 10 FPGA Stratix® 10 AX FPGA Stratix® 10 Bare Die Stratix® 10 GX FPGA Stratix® 10 SX FPGA Stratix® 10 TX FPGA 2 Days No No English Offering Brief Production Windows,Linux a1JUi000009ZcJlMAK Solid understanding of digital design and RTL concepts. Practical experience with a UVM verification environment. Familiarity with simulation tools. Designers that want to integrate AI Agent technology into their verification workflows. Engineering Managers and Technical Leads evaluating AI-driven verification strategies for their organizations, What's Included PDF of slides, lab manual and lab files where applicable Ordering Information Leveraging AI Agents for SoC Verification a1JUi000009ZcJlMAK Production EDA Tools / IDE Education / Training a1MUi00000GbNhBMAV a1MUi00000GbNhBMAV Member 2026-07-16T20:45:12.000+0000 This course prepares system architects, hardware engineers, and software engineers to apply AI agents and large language model (LLM) technology directly within their System-on-Chip (SoC) verification flows. Partner Solutions