Error(13452): Verilog HDL Module Instantiation error at pll_hdmi_reconfig.v(35): module "altera_pll_reconfig_top" has no parameter named "WAIT_FOR_LOCK". - Error(13452): Verilog HDL Module Instantiation error at pll_hdmi_reconfig.v(35): module "altera_pll_reconfig_top" has no parameter named "WAIT_FOR_LOCK". Description Due to a problem in the Intel® Quartus® Prime Pro Edition Software version 21.3 and earlier, the error below will be seen when merging the HDMI Intel® Arria® 10 FPGA IP Design Example and the DisplayPort Intel® Arria® 10 FPGA IP Design Example into a single project. Error(13452): Verilog HDL Module Instantiation error at pll_hdmi_reconfig.v(35): module "altera_pll_reconfig_top" has no parameter named "WAIT_FOR_LOCK". Resolution To work around this problem in current versions of the Intel® Quartus® Prime Design Software, please replace the library option from 'altera_pll_reconfig_XXX' to 'pll_hdmi_reconfig' in the pll_hdmi_reconfig.qip file. Custom Fields values: ['novalue'] Troubleshooting 15010311347 False ['DisplayPort', 'HDMI'] ['FPGA Dev Tools Quartus® Prime Software Pro'] No plan to fix 21.3 ['Arria® 10 FPGAs and SoCs', 'Cyclone® 10 FPGAs', 'Stratix® 10 FPGAs and SoCs'] ['novalue'] ['novalue'] ['novalue']