Why doesn't the clock frequency shown in Table 1-9. Recommended Device Family Speed Grades of the IP Compiler for PCI Express User Guide match the clock frequency shown in the IP GUI? - Why doesn't the clock frequency shown in Table 1-9. Recommended Device Family Speed Grades of the IP Compiler for PCI Express User Guide match the clock frequency shown in the IP GUI? Description The clock frequency shown in Table 1-9. Recommended Device Family Speed Grades of the IP Compiler for PCI Express® User Guide does not match the clock frequency shown in the IP GUI, as the table details the IP Internal Clock Frequency, while the IP GUI details the user side Application clock frequency. Custom Fields values: ['novalue'] Troubleshooting novalue False ['PCI Express'] ['novalue'] novalue novalue ['Arria® II GX FPGA', 'Arria® II GZ FPGA', 'Cyclone® II FPGAs', 'Cyclone® III FPGAs', 'Cyclone® IV GX FPGA', 'Stratix® II FPGAs', 'Stratix® II GX FPGA', 'Stratix® III FPGAs', 'Stratix® IV E FPGA', 'Stratix® IV GX FPGA'] ['novalue'] ['novalue'] ['novalue']