Why do I get timing analysis warnings when compiling the IP Compiler for PCI Express on Stratix IV? - Why do I get timing analysis warnings when compiling the IP Compiler for PCI Express on Stratix IV? Description When running timing analysis of the IP Compiler for PCI Express ® on Stratix ® IV, you will see warnings related to the auto-generated Synopsys Design Constraint (SDC) file. Resolution To resolve each timing analysis constraint warning, follow the workaround for the altera_pci_express.sdc file listed below. [Warning] Warning (332174): Ignored filter at altera_pci_express.sdc(14): *refclk_export could not be matched with a port or pin or register or keeper or net [Workaround] Change altera_pci_express.sdc line 14 from create_clock -period "100 MHz" -name {refclk_pci_express} {*refclk_export} to create_clock -period "100 MHz" -name {refclk_pci_express} [get_ports PCIE_REFCLK] [Warning] Warning (332174): Ignored filter at altera_pci_express.sdc(18): *central_clk_div0* could not be matched with a clock Warning (332174): Ignored filter at altera_pci_express.sdc(18): *_hssi_pcie_hip* could not be matched with a clock [Workaround] Change altera_pci_express.sdc line 18 from set_clock_groups -exclusive -group [get_clocks { *central_clk_div0* }] -group [get_clocks { *_hssi_pcie_hip* }] to set_clock_groups -exclusive -group [get_clocks *central_clk_div0* ] -group [get_clocks *_hssi_pcie_hip* ] This issue will not be fixed in a future software release. Custom Fields values: ['novalue'] Troubleshooting novalue True ['novalue'] ['FPGA Dev Tools Quartus II Software'] novalue 13.0.1 ['Stratix® IV FPGAs', 'Stratix® IV GX FPGA'] ['novalue'] ['novalue'] ['novalue']