Why does my gate level simulation not match my RTL simulation in some cases of inferred RAMs with the combination of registered write-address and registered memory output? - Why does my gate level simulation not match my RTL simulation in some cases of inferred RAMs with the combination of registered write-address and registered memory output? Description Due to a problem in the Intel® Quartus® Prime Pro Edition Software version 21.4 and earlier, you might see the gate level simulation of your M20K RAM is functionally incorrect while performing simultaneous read and write (Read-during-write (RDW)) of the memory. Resolution To work around this problem, perform either one of these steps: Implement the RAM in MLABs or logic Avoid performing RDW operations This problem is scheduled to be fixed in a future release of the Intel® Quartus® Prime Pro Edition Software. Custom Fields values: ['novalue'] Troubleshooting 14015054109 False ['novalue'] ['FPGA Dev Tools Quartus® Prime Software Pro'] 22.1 21.3 ['Programmable Logic Devices'] ['novalue'] ['novalue'] ['novalue']