Why are the strobe_out and strobe_out_n signals placed in non-adjacent pins when using the complementary strobe in the PHY Lite for Parallel Interfaces Intel® Arria® 10 FPGA IP? - Why are the strobe_out and strobe_out_n signals placed in non-adjacent pins when using the complementary strobe in the PHY Lite for Parallel Interfaces Intel® Arria® 10 FPGA IP? Description Due to a problem in PHY Lite for Parallel Interfaces Intel® Arria® 10 FPGA IP, the strobe_out and strobe_out_n signals are placed in non-adjacent pins when you select complementary strobes and compile the design without pin location assignments. Resolution To work around this problem, assign the pin locations of the strobe_out and strobe_out_n signals by placing them to the adjacent DQS/DQSn pins. Custom Fields values: ['novalue'] Troubleshooting 1508524655 False ['PHY Lite for Parallel Interfaces Arria® 10 FPGA IP'] ['FPGA Dev Tools Quartus® Prime Software Pro', 'FPGA Dev Tools Quartus® Prime Software Standard'] novalue 17.0 ['Arria® 10 FPGAs and SoCs'] ['novalue'] ['novalue'] ['novalue']