Cyclone® V GT FPGA - Cyclone V GT FPGA is FPGA industry’s low cost and power for 6.144 Gbps transceiver applications. Product Pages Broadcast Test Wireline Overview Cyclone V GT FPGA is FPGA industry’s low cost and power for 6.144 Gbps transceiver applications. Cyclone V GT FPGA Product Table Benefits Built on TSMC's 28 nm low-power (28LP) process technology, including an abundance of hard intellectual property (IP) blocks, allowing you to differentiate and do more. Do More with Less Power, Design Time, and Cost It offers an 8-input adaptive logic module (ALM) and variable-precision digital signal processing (DSP) blocks, allowing up to 13.59 megabits (Mb) of embedded memory. Logic Integration and Differentiation Capabilities With hard memory controllers, leverage increased transceiver bandwidth capacity ranging from 614 Mbps to 3.125 Gbps. Increased bandwidth capacity Key Features M10K: 10-kilobits (Kb) memory blocks with soft error correction code (ECC). Memory logic array block (MLAB): 640-bit distributed LUTRAM where you can use up to 25% of the ALMs as MLAB memory. Internal memory blocks 875 megabits per second (Mbps) low-voltage differential signaling (LVDS) receiver and 840 Mbps LVDS transmitter. 400 MHz/800 Mbps external memory interface. On-chip termination (OCT). 3.3 V support with up to 16 mA drive strength. General-purpose I/Os Embedded internal coefficient memory, and adder/subtractor for improved efficiency. Memory controller: DDR3, DDR2, and LPDDR2 with 16 and 32-bit ECC support. Embedded hard IP blocks Cyclone V devices deliver the industry’s lowest power 6.144 Gbps transceivers at an estimated 88 mW maximum power consumption per channel. Low-power serial transceivers Applications Ethernet and protocol bridging Wireline High-speed video transport Broadcast and Pro AV Signal capture and analysis Test and Measurement Dev Kits, IP, Example Designs & Software Get Started: Development Kits, IP, Example Designs and Software Dev Kit Cyclone V GT FPGA Development Kit High-speed serial and clock management evaluation. IP High-Speed Transceiver IP Supports multi-protocol high-speed serial connectivity. Clock Management IP Manages timing closure for complex serial interfaces. Example Designs FPGA Developer Site GitHub site that provides a single location for developers to find and use Altera example designs, software, drivers, and associated collateral. Example Design Store This site offers essential FPGA developer resources—including example designs, documentation, and software tools—to accelerate your design process and reduce time to production. Software Quartus® Prime Standard Edition Design Software Quartus® Prime Lite Edition Design Software Documentation Documents Documentation Cyclone V FPGA Product Table Cyclone V Featured Documentation - Quick Links Guide Cyclone V GT FPGA Device Overview Cyclone V FPGA Device Data Sheet Support Resources Cyclone® V GT FPGA