Error (10232): Verilog HDL error at bitec_dp_rx_ss_audio.v(420): index 64 cannot fall outside the declared range [63:0] for vector "fifo_data_x2chan_mux" - Error (10232): Verilog HDL error at bitec_dp_rx_ss_audio.v(420): index 64 cannot fall outside the declared range [63:0] for vector "fifo_data_x2chan_mux" Description Due to a problem in the Quartus® II software version 14.0, you may see this error when compiling a design that contains the DisplayPort IP that has more that 2 Audio receive channels enabled. Resolution To work around this problem in the Quartus® II software version 14.0, replace the existing file < IP variation name >/bitec_dp/rx/ss/bitec_dp_rx_ss_audio.v with the attached version of this file. bitec_dp_rx_ss_audio.v This problem has been fixed starting in the v14.1 release of the Quartus® II software. Custom Fields values: ['novalue'] Troubleshooting 1408036088 False ['DisplayPort IP'] ['FPGA Dev Tools Quartus II Software'] 14.1 14.0 ['Arria® V FPGAs and SoCs', 'Cyclone® V FPGAs and SoCs', 'Stratix® V FPGAs'] ['novalue'] ['novalue'] ['novalue']