Why is incorrect data rate set in the Serial Lite IV IP when generating F-Tile Serial Lite IV Intel® FPGA IP on Windows? - Why is incorrect data rate set in the Serial Lite IV IP when generating F-Tile Serial Lite IV Intel® FPGA IP on Windows? Description Due to a problem in the Intel® Quartus® Prime Pro Edition Software version 22.1 and earlier, you might see an incorrect data rate is set in the Serial Lite IV IP when generating F-Tile Serial Lite IV Intel® FPGA IP on Windows. You can check it with the ' EHIP_DATA_RATE ' parameter in the following generated files: <ip_name>\sl4_f_500\synth\hip\sl4_hip_<ip_name>_sl4_f_500_***.sv <ip_name>\sl4_f_500\synth\hip\ sl4_hip_bb_<ip_name>_sl4_f_500_***.sv This may cause a Support-Logic Generation error when compiling design including F-Tile Serial Lite IV Intel FPGA IP. This problem doesn't happen on Linux. Resolution A patch is available to fix this problem for the Intel Quartus Prime Pro Edition Software version 22.1. Download and install Patch 0.19 from the following links: Patch 0.19 for Windows (quartus-22.1-0.19-windows.exe) Readme for patch 0.19 (quartus-22.1-0.19-readme.txt) This problem is fixed beginning with the Intel® Quartus® Prime Pro Edition Software version 22.3. Custom Fields values: ['novalue'] Troubleshooting 14016693725 False ['novalue'] ['FPGA Dev Tools Quartus® Prime Software Pro'] 22.3 22.1 ['Agilex™ 7 FPGA I-Series'] ['novalue'] ['novalue'] ['novalue']