Why does the Ethernet 10G MAC Intel® FPGA IP's XGMII interface output last few bytes of data with unknown state in simulation? - Why does the Ethernet 10G MAC Intel® FPGA IP's XGMII interface output last few bytes of data with unknown state in simulation?
Description You may encounter above problem if the csr_reset signal of Ethernet 10G MAC Intel® FPGA IP did not toggle once after the start of simulation. Resolution To work around this problem, the csr_reset signal must be toggled once at the beginning of simulation.
Custom Fields values:
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Troubleshooting
FB: 585764;
False
['Ethernet 10G MAC IP']
['FPGA Dev Tools Quartus® Prime Software Pro']
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17.1
['Arria® II FPGAs', 'Arria® V FPGAs and SoCs', 'Cyclone® IV FPGAs', 'Cyclone® V FPGAs and SoCs', 'Stratix® IV FPGAs', 'Stratix® V FPGAs']
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['novalue'] - 2022-12-22
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