Is there any error regarding the Intel® Stratix® 10 L- and H-Tile Standard PCS data rate support in user guide - Is there any error regarding the Intel® Stratix® 10 L- and H-Tile Standard PCS data rate support in user guide Description In the document of the Intel® Stratix® 10 L- and H-Tile Transceiver PHY User Guide (UG-20055 | 2019.10.25) chapter 1 Table 5 , it indicates Standard PCS data rate supports for L-tile -2 Speed Grade and H-tile -1/-2 Speed Grade is 10.81344 Gbps. This is incorrect for maximum data rate support. Resolution The data rate supporting above can be up to 12 Gbps with proper Intel® Stratix® 10 L- and H-Tile Transceiver Native PHY FPGA IP parameter setting. The document is updated in version 20.4 Custom Fields values: ['novalue'] Troubleshooting 1507371848 True ['novalue'] ['FPGA Dev Tools Quartus® Prime Software Pro'] 20.4 19.1 ['Stratix® 10 GX FPGA', 'Stratix® 10 MX FPGA', 'Stratix® 10 SX FPGA', 'Stratix® 10 TX FPGA'] ['novalue'] ['novalue'] ['novalue']