Placement constraints for PLL in QPP - Placement constraints for PLL in QPP There is the feature called as logic lock which can fix placement of a node, I want to know if it is possible to use logic lock for fixing position of PLL? I get a warning in plan stage of fitter as "ATX/FPLL is not placed in the same bank as reference clock." Device family: Arria 10 Replies: Re: Placement constraints for PLL in QPP Hi, I'm able to place the node in the assignment editor, select location option and provide the desired HSSIPMA location which was found through the Chip Planner. My question now is that the PLL is actually part of a hard IP. Which is spread across various blocks. How do I take that hard IP to move it to some other location? Replies: Re: Placement constraints for PLL in QPP Hi, I really regret my delayed response. I'll be replying back to you within next 48 hours on if your latest suggestion helps me. Replies: Re: Placement constraints for PLL in QPP As we do not receive any response from you on the previous reply provided. Please login to ‘ https://supporttickets.intel.com/s/?language=en_US ’, view details of the desire request, and post a feed/response within the next 15 days to allow me to continue to support you. After 15 days, this thread will be transitioned to community support. The community users will be able to help you on your follow-up questions. Replies: Re: Placement constraints for PLL in QPP Hello, I wish to follow up with you regarding the issue. Do you able to moving forward with the recommendation? Or do you need more support on this? Regards, Aqid Replies: Re: Placement constraints for PLL in QPP You can choose "Location" for that version of Quartus Prime. Replies: Re: Placement constraints for PLL in QPP There's no "Placement" option in the assignment name drop-down. QPP 20.1 Replies: Re: Placement constraints for PLL in QPP Hi, I don't think that is the correct cmd in the qsf that relates with the PLL placement. You can check Assignment Editor. From there, you can choose the PLL pin --> choose Placement in the Assignment Name --> choose the PLL that locate in the same bank with the reference clock. https://www.intel.com/content/www/us/en/programmable/quartushelp/current/index.htm#assign/ase/ase_com_assign_ed.htm Replies: Re: Placement constraints for PLL in QPP If I refer QPP settings file reference manual, what type of settings should be used to ensure desired PLL placement? Replies: Re: Placement constraints for PLL in QPP I could see following cmd in qsf file: set_instance_assignment -name RESERVE_REGION "coordinates" -to PLL_instance. set_instance_assignment -name RESERVE_PLACE_REGION OFF -to PLL_instance For the second cmd, I changed it to ON and reran the Fit - Plan, but still same message is displayed. Replies: Re: Placement constraints for PLL in QPP Will try this and let you know. Replies: Re: Placement constraints for PLL in QPP From my opinion, logic lock will reduce the flexibility for you on the timing side of the design. My suggestion is you need to change the PLL location through the qsf assignments.