MIPI DP 2.0 - The MIPI DisplayPort 2.0 IP Core is a next-generation high-speed display interface IP solution designed to meet the increasing demands for ultra-high-resolution video, multi-stream support, and power… Agilex™ 3 FPGA C-Series Agilex™ 5 FPGA D-Series Agilex™ 5 FPGA E-Series Agilex™ 7 FPGA F-Series Agilex™ 7 FPGA I-Series Agilex™ 7 FPGA M-Series The MIPI DisplayPort 2.0 IP Core is a next-generation high-speed display interface IP solution designed to meet the increasing demands for ultra-high-resolution video, multi-stream support, and power efficiency across a broad spectrum of devices. Built on the latest DisplayPort 2.0 specification from the Video Electronics Standards Association (VESA), it delivers enhanced data bandwidth, flexible protocol layers, and superior display quality—all while supporting MIPI PHY standards such as M-PHY for mobile and embedded applications. ASIC Proto Broadcast Consumer Defense Government Industrial Medical Test Transportation MIPI DP 2.0 Key Features Supports SST as well as MST to split streams for daisy chaining multiple displays. Offering Brief No No No Yes Encrypted Verilog Verilog Agilex™ 3 FPGA C-Series Agilex™ 5 FPGA D-Series Agilex™ 5 FPGA E-Series Agilex™ 7 FPGA F-Series Agilex™ 7 FPGA I-Series Agilex™ 7 FPGA M-Series Yes Yes 24.3.1 Offering Brief Production a1JUi000007WCA8MAO What's Included Reference design and integration guidelines Ordering Information QB-IP-MIPI-DP-2.0 a1JUi000007WCA8MAO Production Intellectual Property (IP) a1MUi00000BOWpkMAH a1MUi00000BOWpkMAH Member 2026-03-05T05:28:40.000+0000 The MIPI DisplayPort 2.0 IP Core is a next-generation high-speed display interface IP solution designed to meet the increasing demands for ultra-high-resolution video, multi-stream support, and power efficiency across a broad spectrum of devices. Partner Solutions