When using the R-Tile Avalon Streaming IP for PCI Express* how should the CPL Always Grant option be used? - When using the R-Tile Avalon Streaming IP for PCI Express* how should the CPL Always Grant option be used? Description CPL Always Grant is a new option in the GUI for the R-Tile Avalon Streaming IP for PCI Express. If the parameter is turned on, internally generated TLPs (completion and message) will check for available credits at the link partner (i.e., total credit) and will not be limited to the locally allocated credit of 1, 4, or 16, depending on the scale factor used. If the parameter is turned off, which is the default: Consider that there are 100 completion credits available and we allocated 4 credits for internally generated completions. After 4 config reads are received and after the Hard IP has sent 4 completions in response, the 5th config read received will not result in a completion being transmitted by the Hard IP until a credit update is received from the Root Port, even though the Hard IP still has 96 credits available for completions. This behaviour applies only to configuration requests which require completions to be generated by the PCIe Hard IP. Internally generated messages are posted and do not require completions to be generated. The FC_Update check is not bypassed when the CPL Always Grant option is turned on. The Hard IP keeps track of available credits at the link partner and prevents any TLPs (internal or user- generated) from being transmitted through the link enough credits are not available. For header and data, the credits reserved for internal IP usage are 1, 4, and 16 for scaling factors of 1, 4, and 16 respectively. Header credits and data credits have their own allocation. For new designs targeting an interoperable vendor-neutral system architecture, Altera recommends that this option be enabled. Resolution This information is scheduled to be included in a future release of the R-Tile Avalon Streaming IP for PCI Express User Guide. Custom Fields values: ['novalue'] Troubleshooting CEG-4708 No ['Interfaces PCIe'] ['FPGA Dev Tools Quartus® Prime Software Pro'] novalue 25.3 ['Agilex™ 7 FPGAs and SoCs', 'Agilex™ 9 FPGAs and SoCs'] ['novalue'] ['novalue'] ['novalue']