Best Design Practices for Timing Closure - 50 Minutes Learn how to address timing closure issues with HDL design techniques. This training will discuss the problem of timing closure and why it is important to plan for it. You will learn about common timing closure issues. You will see how to fix example timing closure situations by changing how the functionality is coded. You will learn how the Altera® Quartus® Prime Design Software can assist you with this goal. Course Objectives At course completion, you will be able to: Identify HDL constructs that can cause problems in timing closure Address such issues by suitable changes in the HDL code Skills Required Background in digital logic design an understanding of Basic FPGA design flow Basic understanding of the Altera® Quartus Prime user interface Basic understanding of Verilog HDL or VHDL coding If the audio for the course does not start automatically, press pause and then play on the course player. The transcript of the course audio is available in the Notes or closed captioning (CC) feature of the player. If you need assistance with this course, please email fpgatraining@altera.com . Reference Course Code: FPGA_OHDL1130. FPGA_OHDL1130. <p>Best Design Practices for Timing Closure</p>