Post-fit simulation for designs that target Arria V and Cyclone V devices with HPS IP atoms might function incorrectly - Post-fit simulation for designs that target Arria V and Cyclone V devices with HPS IP atoms might function incorrectly Description If your design targets an Arria V or Cyclone V device and includes hard processor system (HPS) IP atoms, post-fit simulation might function incorrectly under the following circumstances: If the hps2fpga interface data width is configured to 32 or 128 bits If the fpga2hps interface data width is configured to 32 or 128 bits If the hps2fpga user clocks output frequencies are other than 100 MHz Resolution Update the Verilog Output File ( .vo ) generated by the EDA Netlist Writer prior to post-fit simulation, as follows: Add a parameter named DATA_WIDTH and set the value to either 32, 64 or 128 according to the hps2fpga Advanced eXtensible Interface (AXI) data width. Add a parameter named DATA_WIDTH and set the value to either 32, 64, or 128 according to the fpga2hps AXI data width. Add parameters named H2F_USER0_CLK_FREQ , H2F_USER1_CLK_FREQ and H2F_USER2_CLK_FREQ . Set the values of these parameters according to the frequencies of the h2f_user0_clk , h2f_user1_clk and h2f_user2_clk user clocks, respectively. Custom Fields values: ['novalue'] Troubleshooting novalue True ['novalue'] ['FPGA Dev Tools Quartus II Software'] 13.0 12.1 ['Arria® V FPGAs and SoCs', 'Cyclone® V FPGAs and SoCs'] ['novalue'] ['novalue'] ['novalue']