Why do the GTS HDMI IP, GTS SDI II IP, and GTS DisplayPort PHY IP fail during compilation when multiple Dual Simplex Groups are combined into a single Dual Simplex Group, but there is no error/warning shown? - Why do the GTS HDMI IP, GTS SDI II IP, and GTS DisplayPort PHY IP fail during compilation when multiple Dual Simplex Groups are combined into a single Dual Simplex Group, but there is no error/warning shown? Description Due to a problem in the Quartus® Prime Pro Edition Software version 24.2, when using the Agilex™ 5 FPGA devices with multiple Dual Simplex Groups combined into a single Dual Simplex Group, a compilation error will occur without any error/warning message in the Dual Simplex assignment editor. Resolution It is recommended to separate the arrangement based on multiple Dual Simplex Groups and not combine in single Dual Simplex Group. Manually check and rearrange the Dual Simplex Groups accordingly if the compilation fails. This problem is fixed beginning with version 24.3 of the Quartus® Prime Pro Edition Software. Custom Fields values: ['novalue'] Troubleshooting 15016087439 False ['HDMI'] ['FPGA Dev Tools Quartus® Prime Software Pro'] 24.3 24.2 ['Agilex™ 5 FPGAs and SoCs'] ['novalue'] ['novalue'] ['novalue']