Why am I seeing readback data corruption on my “Ethernet Reconfiguration” client interface of the F-tile Ethernet Intel® FPGA Hard IP? - Why am I seeing readback data corruption on my “Ethernet Reconfiguration” client interface of the F-tile Ethernet Intel® FPGA Hard IP? Description Due to a problem in the Intel® Quartus® Prime Pro Edition Software version 23.1, readback data corruption on the “Ethernet Reconfiguration” client interface of the F-tile Ethernet Intel® FPGA Hard IP will occur if the Avalon memory-mapped interface read transaction is in progress when both the i_rst_n and i_reconfig_reset are asserted simultaneously. In this event, the first data being read back from the underlying Ethernet hard IP will be invalid. Resolution To work around this problem, if i_rst_n and i_reconfig_reset are asserted simultaneously during an Avalon memory-mapped interface read transaction to the underlying the F-tile Ethernet Intel FPGA Hard IP, you should ignore the readback data of the first read transaction and perform an additional read to the same location in order to obtain the proper readback data value. Custom Fields values: ['novalue'] Troubleshooting 16019995960 False ['novalue'] ['FPGA Dev Tools Quartus® Prime Software Pro'] novalue 23.1 ['Agilex™ 7 FPGAs and SoCs'] ['novalue'] ['novalue'] ['novalue']