Why can't the Parallel Flash Loader II Intel® FPGA IP configure Intel® Stratix® 10 devices? - Why can't the Parallel Flash Loader II Intel® FPGA IP configure Intel® Stratix® 10 devices? Description The Paraller Flash Loader II Intel® FPGA IP (PFLII IP) will first check if CONF_DONE is low. The IP will not proceed with configuration if it is already high. This is why the PFLII IP cannot configure Intel® Stratix® 10 devices. Resolution Check if CONF_DONE is pulled up as CONF_DONE and INIT_DONE are no longer required to be pulled up to VCCIO_SDM . Note that SDMIO_0 and SDM_16 are initially pulled down. Hence an intermediate voltage level by pull-up and internal pull-down resister might cause configuration failure when using the PFLII IP. PFLII IP monitors CONF_DONE signal low as start condition of operation. This requirement has been changed for Intel® Stratix® 10 devices. Custom Fields values: ['novalue'] Troubleshooting FB: 482181; False ['novalue'] ['FPGA Dev Tools Quartus® Prime Software'] novalue 17.0 ['Stratix® 10 FPGAs and SoCs'] ['MicroBlaster™ Fast Passive Parallel Software Driver'] ['novalue'] ['novalue']