Why does Agilex® 5 FPGA and Agilex® FPGA 3 HVIO PLL fail to lock after reconfiguration? - Why does Agilex® 5 FPGA and Agilex® FPGA 3 HVIO PLL fail to lock after reconfiguration? Description HVIO PLL reconfiguration may require word-addressed register offsets for Agilex® 5 FPGA and Agilex® 3 FPGA devices. The HVIO PLL reconfiguration registers for Agilex 5 and Agilex 3 devices are documented using byte offsets, but the Avalon® Memory‑Mapped (Avalon‑MM) interface expects word-addressed offsets. Using the documented byte offsets directly on the address bus can cause incorrect register access, which prevents the PLL from recovering after it loses lock during reconfiguration. Resolution Apply the following workaround to ensure correct HVIO PLL reconfiguration: Use word-addressed offsets when accessing HVIO PLL registers through the Avalon-MM interface. Convert documented byte offsets to word offsets by dividing by 4 before driving the address bus. Update the register address mapping in your design accordingly. Example: localparam [8:0] ENABLE_RW_ADDR = 9'h10 >> 2; // 0x04 localparam [8:0] ENABLE_RECAL_ADDR = 9'h48 >> 2; // 0x12 localparam [8:0] CLK_GATING_ADDR = 9'h54 >> 2; // 0x15 localparam [8:0] CLEAR_STATUS_ADDR = 9'h58 >> 2; // 0x16 localparam [8:0] C0_ADDR = 9'h5C >> 2; // 0x17 localparam [8:0] C1_ADDR = 9'h60 >> 2; // 0x18 localparam [8:0] RESET_ADDR = 9'h80 >> 2; // 0x20 localparam [8:0] RECAL_ADDR = 9'h88 >> 2; // 0x22 Custom Fields values: Troubleshooting QS-603021 novalue novalue 25.3.1 ['Agilex® 3 FPGAs and SoCs', 'Agilex® 5 FPGAs and SoCs']