News at Embedded World 2025 - Learn about Altera at Embedded World to see the latest innovations about the transformative impact of AI at the Edge for embedded solutions. Altera @ Embedded World 2025 March 11 - 13 | Nürnberg, Germany | Join us at Booth #5-343 Join Sandra Rivera, CEO of Altera, at Embedded World 2025 to explore the transformative impact of AI at the Edge. Discover how FPGAs revolutionize AI implementation with programmable hardware and software solutions. Sandra will discuss AI's progression at the Edge, addressing security, low latency, low power, and cost. Learn how AI models transition from frameworks to deployable solutions, meeting the demands of Edge applications. Get a free ticket using Altera's voucher code: Code: ew25548104 Pushing Boundaries: Flexible AI at the Edge Embedded World Demo Preview Cost-optimized devices (MAX® 10 FPGAs) demonstrate low-latency AI preprocessing needed to detect defects, detect objects, and monitor real-time conditions. Analyzing MIPI/HDMI data coincident with the camera sensor, Altera partner ONE WARE created an edge solution requiring minimal infrastructure and energy while delivering the needed performance. AI: Low Power Quality Inspection This demo shows an FPGA-based image signal processing solution with state-of-the-art object detection and pose estimation utilizing the Agilex™ 5 FPGAs’ enhanced DSP AI Tensor Blocks. It also shows the easy-to-use design flow of FPGA AI Suite and Video and Vision Processing Suite IP AI: 4K AI-enabled Camera In this demo from Altera partner El Camino, visitors test their drawing skills to see if a trained ResNet50 model recognizes hand drawings. A camera’s HDMI output is tapped, preconditioned, and input to the AI inference engine within an Agilex™ 7 FPGA. The FPGAs ARM SoC (Linux) reports the live results. The design flow combines FPGA IP, AI software, and Embedded software AI: Sketch Recognition on SoC FPGA Achieve low-latency AI inferencing using Altera's FPGA AI Suite in parallel to other edge functions, such as image processing. Depending on your performance, power, and cost requirements, Altera's AI-infused architectures offer multiple product families to get to market quickly while simplifying your AI solution. AI: Real-Time AI Facial Recognition Agilex™ 7 FPGAs provide high-performance, low-latency video processing to ingest, process, and output video up to 8Kp60. Operating at 600MHz, the video system is a modular, flexible, and customizable design using Video Connectivity IP and Video and Vision Processing Suite IP. High Performance 8K Video & Vision Processing Agilex™ 5 FPGAs features map nicely to 4K multi-sensor camera requirements: integrated MIPI, Display Port, and HDMI interfaces, plus support for modular Image Signal Processors using advanced features such as HDR fusion, tone mapping, and adaptive noise reduction. Multi-sensor 4K HDR Camera Imaging Agilex™ 5 SoC FPGAs are capable of robotic control and path planning in a single device. This design combines software functions and hardware drive control while the FPGA communicates with the robot using ROS 2 messaging protocols. Robot control with ROS 2 on a SoC FPGA Agilex™ FPGA families provide hardened security solutions, including attestation, which interrogates the system to prove its identity and configuration. Attestation works with other device security features, such as authentication, providing an additional layer of security to ensure each FPGA is operating as intended. Attestation: The next layer of security Altera partner Accelerat software shows a complete flow for the definition, configuration, and deployment of mixed-criticality applications using the Agilex™ 5 FPGA heterogenous quad-core ARM Subsystem to host multiple Operating Systems with different levels of safety and security. Mixed-Criticality Safety Host System This demo shows a dual-axis motor control design that implements functional safety. The TÜV-approved Cat. 3 PL d safety architecture is applied to this design, which uses dual-channel safety checkers running in FPGA logic and on the embedded ARM CPUs. Drive-on-Chip demo with Cat. 3 PL d safety Altera Partners