Why does the rx_latency_adj_10g and tx_latency_adj_10g signal descriptions refer to 1g for the Arria V and Stratix V devices in the Altera Transceiver PHY IP User Guide? - Why does the rx_latency_adj_10g and tx_latency_adj_10g signal descriptions refer to 1g for the Arria V and Stratix V devices in the Altera Transceiver PHY IP User Guide? Description Due to a mistake in "Table 3-13: 10GBASE-R Status, 1588, and PLL Reference Clock Outputs" of the Altera® Transceiver PHY IP Core User Guide (PDF) the rx_latency_adj_10g and tx_latency_adj_10g signals refer to 1g for the Arria® V and Stratix® V devices. The rx_latency_adj_10g and tx_latency_adj_10g signal signals should only refer to 10g. Resolution This problem will be fixed in a future version of the Transceiver PHY User Guide (PDF). Custom Fields values: ['novalue'] Troubleshooting novalue False ['novalue'] ['FPGA Dev Tools Quartus II Software'] novalue 13.1 ['Arria® V GT FPGA', 'Arria® V GX FPGA', 'Arria® V GZ FPGA', 'Stratix® V GS FPGA', 'Stratix® V GT FPGA', 'Stratix® V GX FPGA'] ['novalue'] ['novalue'] ['novalue']