Why does the R-Tile AXI Multichannel DMA IP for PCI Express* AXI-S Packet Generate/Check Example Design generation fail with Enable User FLR is selected? - Why does the R-Tile AXI Multichannel DMA IP for PCI Express* AXI-S Packet Generate/Check Example Design generation fail with Enable User FLR is selected? Description Due to a problem in the Quartus® Prime Pro Edition Software versions 25.3 and later, Example Design generation fails for the R-Tile AXI Multichannel DMA IP for PCI Express* when: AXI-S Packet Generate/Check mode is selected Enable User FLR option is selected under the PCIe Settings --> MCDMA Settings tab. The problem is observed a few minutes after clicking the Generate Example Design button. Quartus® Prime Pro Edition Software reports an error in the Generate Example Design Completed window and the Example Design is not generated successfully. An example of the message observed in the Generate Example Design Completed window is shown below: Error: pcie_axi_mcdma_0: Fail .qsys synthesis generation Error: pcie_axi_mcdma_0: Unable to generated HDL Files for the system .qsys Error: Failed to generate example design example_design to: <path> Generate Example Design: completed with errors. This problem applies only to the AXI-S Packet Generator/Checker variant of the Example Design. The AXI Multichannel DMA IP itself can still be generated successfully when the Enable User FLR option is selected. Resolution To work around this problem, do not select the Enable User FLR option when generating the R-Tile AXI Multichannel DMA IP for PCI Express* AXI-S Packet Generate/Check Example Design. There is currently no other workaround for Quartus® Prime Pro Edition Software versions 25.3 and later. This problem is planned to be fixed in a future release of the Quartus® Prime Pro Edition Software. Custom Fields values: Troubleshooting QS-18966 novalue ['Interfaces PCIe'] ['FPGA Dev Tools Quartus® Prime Software Pro'] novalue 25.3 ['Agilex® 7 FPGAs and SoCs']