Why do the Agilex™ 7 FPGA devices fail to reconfigure after the F-tile System PLL reference clock has a temporary loss? - Why do the Agilex™ 7 FPGA devices fail to reconfigure after the F-tile System PLL reference clock has a temporary loss? Description Due to a problem in the Quartus® Prime Pro Edition Software version 23.1 and earlier, if your F-tile System PLL reference clock experiences discontinuity or a temporary loss condition, you might observe that the Agilex™ 7 FPGA device fails to reconfigure. Altera recommends you provide a stable reference clock throughout the design operation once your reference clock for the F-tile System PLL is available. If you cannot adhere to this, you must reconfigure the device. Resolution To work around this problem, you should try configuring your device again if your first reconfiguration fails. Custom Fields values: ['novalue'] Errata 14015049289 False ['novalue'] ['FPGA Dev Tools Quartus® Prime Software Pro'] No plan to fix 22.3 ['Agilex™ 7 FPGA F-Series'] ['novalue'] ['novalue'] ['novalue']